1. Field of the Invention
The present invention relates to a bonded substrate and a manufacturing method thereof, and more specifically to a bonding technology that allows two wafers having different sizes from each other to be bonded without causing any misalignment with respect to other in their orientation flats or notches, facilitates to reduce void otherwise possibly generated between bonding surfaces in an outer peripheral region and further allows an effective area in an active layer of bonded substrate to be expanded.
2. Description of the Related Art
Regarding a bonded substrate made by bonding two wafers having different sizes from each other has been well known such one as disclosed in the cited Patent Document No. 1, for example, as listed below. This type of bonded substrate may be used, for example, in fabricating a SOI (Silicon on Insulator) substrate. The bonded SOI substrate is defined by a substrate comprising an active layer on a surface of which a device is to be formed, and a supporting substrate wafer for supporting said active layer from back side thereof, wherein a silicon oxide film is buried between said active layer and said supporting substrate wafer.
To manufacture the bonded SOI substrate, firstly an active layer wafer covered with a silicon oxide film is bonded with a supporting substrate wafer at a room temperature so as to form a bonded substrate. These two wafers are equally sized. An orientation flat or notch has been formed in an outer peripheral region of each wafer. During this process, the buried silicon oxide film emerges between said two wafers. Secondly, a predetermined bonding heat treatment is applied to the bonded substrate to enhance a bonding strength between two wafers. Subsequently, the grinding or etching process is applied to the outer peripheral region of the active layer wafer to remove any areas of bad bonding existing in the outer peripheral region of the bonded substrate. This is practiced in order to prevent any scars or dusting possibly caused by the bad bonding areas from being developed in a subsequent process. The bonded substrate is thus obtained, which comprises two wafers having different sizes from each other. Subsequently, a surface abrasion or a surface polishing is applied across the active layer wafer to define the active layer as thick as 20 μm, thus fabricating the bonded SOI substrate.
By the way, a bonding surface of each of the active layer wafer and the supporting substrate wafer has been processed into mirror finished surface by the CMP (Chemical Mechanical Polishing) processing. Applying mirror-surface finishing process may cause polish-drop in the outer peripheral region in either of the wafers. Increasing in the degree of polish-drop has been a factor in said problem of the bad bonding area being extended. The area of band bonding is inferior in its mechanical strength to the other area (i.e., an area of complete bonding). Due to this, with a larger area of bad bonding, there will be a higher risk that chipping, wafer stripping and the likes could be induced in subsequent steps, such as a cleaning step and a polishing step, for example. Besides, a width of the bad bonding area in the radial direction of the wafer should be made as narrower as possible, so that an effective area in the active layer wafer (i.e., an area to be used effectively for a device) may be expanded.
To address this, other prior arts to solve the above problem have been known, as disclosed in, for example, the cited Patent Document No. 2 and the cited Patent Document No. 3, as listed below. In the art as disclosed in the same Documents, as shown in FIG. 2, a supporting substrate wafer 11 and an active layer wafer 12 having different sizes from each other are prepared in advance, and they are aligned in their centerlines and bonded together so that an area of bad bonding due to the polish-drop could be consequently reduced. That is, if the wafers 11 and 12 formed in advance to have different sizes from each other are used, they will have different starting points of the drop in the outer peripheral regions in the radial direction of the wafers 11 and 12 during the bonding. Owing to this, the bad bonding area could be reduced by a width “W” (see FIG. 2, S201) as compared with the bonding of two wafers having equal sizes (see FIG. 2, S202). This may help expand an effective area in the active layer wafer 12.
[Patent Document No. 1]
Japanese Patent Publication No. 2535957 (page 1, FIG. 1);
[Patent Document No. 2]
Japanese Patent Laid-open Publication No. H9-213593 (page 1, FIG. 1); and
[Patent Document No. 3]
Japanese Patent Laid-open Publication No. 2000-223683 (page 1, FIG. 1).
However, the cited Patent Documents 2 and 3 have not disclosed any aligning method for aligning said two wafers 11 and 12 during the bonding process. It has not been apparent how the centerline of the supporting substrate wafer 11 is aligned with the centerline of the active layer wafer 12 to bond them together when the supporting substrate wafer 11 is bonded to the active layer wafer 12.
That is, in this case, differently from the Patent Document 1 disclosing the bonding of two wafers 11 and 12 having the same diameters, the supporting substrate wafer 11 and the active layer wafer 12 have different outer diameters from each other. Consequently, it was still difficult to align the two wafers 11 and 12 with their centerlines aligned by simply taking advantage of orientation flats or notches formed in the outer peripheral regions of the wafers 11 and 12. For example, if the orientation flat or the notches of the both wafers 11 and 12 are aligned simply, in most of the cases, the wafers 11 and 12 would be bonded together with their centerlines shifted from each other (i.e., in the eccentric condition).